By Douglas A. Pucknell
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The 1st ebook to house a extensive spectrum of procedure and machine layout, and modelling concerns with regards to semiconductor units, bridging the distance among gadget modelling and approach layout utilizing TCAD. Examples for sorts of Si-, SiGe-, GaAs- and InP-based heterostructure MOS and bipolar transistors are in comparison with experimental information from cutting-edge units.
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Extra info for Basic VLSI Design
A Review of Microelectronics and An Introduction to MOS Technology •• 9. The whole chip then has metal (aluminum) deposited over its surface to a thickness typically of I Jlm. This metal layer is then masked and etched to form the required interconnection pattern. It will be seen that the process revolves around the formation or deposition and patterning of three layers, separated by silicon dioxide insulation. The layers are diffusion within the substrate, polysilicon on oxide on the substrate, and metal insulated again by oxide.
11 Voo RHistor pull-up. •tl ) Basic VLSI Design 2. 12). (a) Dissipation is high ,since rail to rail current flows when V;n = logical 1. d. device. u. device is non-saturated initially and this presents lower resistance through which to charge capacitive loads . ' ~: . No curr nt .... 12 nMOS depletion mode transistor pull-up and transfer characteristic. 3. 13). (a) Dissipation is high since current flows when V;n =logical 1 (VaG is returned to V00) . (b) Vout can never reach VDD (logical I) if VGG = V00 as is normally the case.
The second additional layer-the buried n+ subcollector (BCCD) is added to reduce the n-well (collector) resistance and thus improve the quality of the bipolar transistor. 16. Bipolar transistor characteristics will follow in Chapter 2 and the relevant design rules are dealt with in Chapter 3. 13(t) will serve to further illustrate the actual geometry of a BiCMOS bipolar transistor in n-well technology. 17; which also includes ECL and GaAs gates for cost comparison. 1 BICMOS Fabrication In an n-well Process The basic process steps used are those already outlined for CMOS but with additional process steps and additional masks defining: (i) the p+ base region; (ii) n+ collector area; and (iii) the buried subcollector (BCCD).