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D1) or pins A1 and B2 (Fig. d2) are assigned to the same net. We select the configuration with the smaller difference in the individual Universal Methodology to Handle Differential Pairs during Pin Assignment From Pins A2 A1 B1 B2 To Pins (a) Fat From Pins A B Fat To Pins (b) Fat From Pins From Pins A A1 B B1 Fat To Pins (c) To Pins (d1) 31 From Pins A2 A1 B2 B1 A2 B2 To Pins (d2) Fig. 9. Fat pin transformation and inverse transformation. (a) Pin assignment task for two nets. (b) Transformation from pins to fat pins.

In: Proceedings of the International IEEE Annual Symposium on VLSI, April 2002, pp. : Design and Management of 3D Chip Multiprocessors Using Network-inMemory. In: Proceedings of the IEEE International Symposium on Computer Architecture, June 2006, pp. : 3-D Topologies for Networks-on-Chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(10), 1081–1090 (2007) Universal Methodology to Handle Differential Pairs during Pin Assignment Tilo Meister1, Jens Lienig1, and Gisbert Thomke2 1 2 Dresden University of Technology, Dresden, Germany IBM Research and Development, Böblingen, Germany Abstract.

Subsequently, pin assignment variants 36 T. Meister, J. Lienig, and G. Thomke with more and more differential pairs are created, until the best pin assignment for the design is found. 5 Experimental Results The effectiveness of the presented methodology is proven by comparing pin assignments with differential pairs to those without differential pairs. First, results from PAAs (without differential pairs) applied to industrial designs are reported. Next, these PAAs are extended by the fat pin methodology to include differential pairs.

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